Atomic layer etching is a precision technique that removes materials in self limited steps, enabling angstrom level control, smooth surfaces, and damage minimization. This article covers the Top 10 Atomic Layer Etching Use Cases in Semiconductor FEOL and BEOL with a practical focus on why and how each case benefits device scaling. You will learn where ALE outperforms conventional plasma etch, how chemistries and cycles are tuned, and what metrology confirms success. The goal is to help basic and advanced learners connect process intent to integration needs, so decisions align with yield, reliability, and cost across modern technology nodes.
#1 Gate spacer trimming for FinFET and GAAFET
Atomic layer etching enables accurate gate spacer trimming in FinFET and gate all around devices by cycling adsorption and low energy removal to take away only a few angstroms per cycle. Precise spacer width sets line edge placement for extensions and reduces parasitic capacitance without gouging the silicon fin or nanosheet. Selective chemistries on silicon nitride versus silicon oxide avoid recessing the channel or damaging shallow junctions. With in situ endpoint and post etch ellipsometry, you will maintain uniformity across the wafer while holding within die variation below tight design rules. This improves short channel control and boosts drive current repeatability at advanced nodes.
#2 Channel recess and epitaxy interface preparation
For channel recess and source drain epitaxy interface preparation, atomic layer etching allows angstrom level removal of silicon germanium or silicon with excellent selectivity to nearby oxides and nitrides. The self limited nature keeps the recess flat and smooth, which lowers interface trap density and supports uniform stress transfer from epitaxial SiGe or SiC. By choosing halogen adsorption followed by low energy activation, you will desorb only the reacted monolayer and prevent plasma damage. Tight recess depth control improves threshold voltage targeting and reduces variability. Metrology with cross sectional TEM and spectroscopic ellipsometry confirms surface quality before epitaxy.
#3 Contact etch stop layer and stress liner tuning
Contact etch stop layers and stress liners require careful tuning to balance pattern transfer and device stress. Atomic layer etching enables highly selective thinning of silicon nitride or silicon carbide without degrading adjacent oxides, low k dielectrics, or the silicon surface. Because each cycle removes a controlled fraction of a nanometer, you will dial in residual film thickness that preserves stress while easing subsequent contact or via etches. Low ion energy minimizes roughness and defect creation, which supports lower leakage and improved time dependent dielectric breakdown margins. Inline reflectometry and sheet resistance mapping verify that the target liner properties have been achieved.
#4 Hard mask opening with low k protection
In pattern transfer stacks that use hard masks, atomic layer etching provides a gentle route to open silicon nitride, amorphous carbon, or metal hard masks with selectivity to fragile low k interlayer dielectrics. Conventional continuous plasma can cause sidewall roughness and microtrenching, while ALE limits removal to a reacted layer per cycle, keeping profiles vertical and corners sharp. This improves line width roughness and pattern fidelity for dense metal lines. Careful selection of adsorption precursors and activation energy lets you preserve porosity and mechanical strength in low k films. Critical dimension uniformity improves across large wafers, raising BEOL yield.
#5 Self aligned contact and cut mask cleanup
Self aligned contact and cut mask flows benefit from atomic layer etching to clean residual spacers, remove very thin liner fences, and tune selective recesses that prevent shorts. ALE steps can target silicon nitride or oxide with chemistry that ignores the underlying gate or channel materials. Because removal per cycle is fixed, you will avoid catastrophic overetch when local microloading varies. Improved selectivity reduces need for aggressive overetch margins, which protects critical dimensions and improves line edge placement. Electrical test data often shows lower contact resistance variability and fewer leakage failures when ALE replaces a portion of continuous plasma etch.
#6 High k metal gate stack trimming and clean
High k metal gate stacks are sensitive to damage and stoichiometry shifts. Atomic layer etching offers gentle removal of titanium nitride, tantalum nitride, or aluminum containing layers while preserving hafnium oxide and the silicon channel. By combining surface ligand formation with low energy activation, you will strip only the topmost reacted layer, which controls work function tuning and leaves smooth interfaces for subsequent deposition. This helps reduce threshold voltage drift, bias temperature instability, and flicker noise. Process windows become wider because the etch rate saturates per cycle, allowing integration teams to meet both electrical targets and reliability margins simultaneously.
#7 BEOL via profile control and barrier reveal
In BEOL via formation, atomic layer etching assists with profile control and barrier exposure in narrow, high aspect ratio structures. Adsorption and activation cycles remove polymer and a controlled amount of dielectric to reveal tantalum nitride or ruthenium barriers without gouging underlying copper. The gentle approach reduces via deformation and suppresses keyhole formation. Uniform sidewall smoothing lowers electron scattering sites, which reduces line resistance variability. With ALE you will also manage etch bias across dense and isolated patterns, improving overlay margin for subsequent metal fill. Long term electromigration reliability benefits from smoother interfaces and reduced plasma induced damage.
#8 Buried power rail and backside power reveal
Emerging buried power rail and backside power integrations demand selective reveal of conductive rails through complex stacks. Atomic layer etching provides atomic scale control to thin dielectrics above rails, expose etch stop layers, and protect fragile ultra low k materials nearby. Because activation energy is low, you will avoid charging damage to transistors that share the wafer. Controlled removal per cycle supports alignment budgets for nano via drilling and metallization. The result is lower series resistance, improved power delivery, and reduced voltage droop during dynamic workloads. Process engineers can couple ALE with atomic layer deposition to build precise multi layer composites.
#9 Two dimensional materials and ferroelectric trimming
Two dimensional materials and ultrathin ferroelectrics are highly sensitive to plasma damage. Atomic layer etching enables edge shaping and thickness trimming of materials like graphene, molybdenum disulfide, and hafnium zirconium oxide with minimal defect creation. Self limited reactions remove only a monolayer equivalent, preserving mobility and polarization. By tailoring adsorption species and activation timing, you will maintain stoichiometry while achieving target thickness and edge roughness. This is valuable for low power logic, sensors, and memory elements where interface quality dominates performance. Raman spectroscopy and piezo response force microscopy verify that functional properties remain intact after controlled atomic trimming.
#10 Post lithography residue removal and LER smoothing
Post lithography cleans and line edge roughness smoothing benefit from atomic layer etching used as a surface conditioning step. Instead of blanket ashing that can roughen features, ALE removes only the reacted molecules and polishes sidewalls atom by atom. This reduces stochastic defects from EUV photoresist while keeping critical dimensions stable. By integrating short cycles between etch and deposition steps, you will accumulate smoother interfaces that scatter fewer carriers and trap fewer charges. The approach raises parametric yield and aids in matching across the die. Metrology with critical dimension scanning electron microscopy confirms reduced roughness and improved linewidth control.